SATURN’s goal is to bridge the current gap between modelling and verification/synthesis in UML based designs of Embedded Systems that are equally composed of hardware and software. To do this, the UML profile for MARTE is evaluated for its complementary application with SysML, and significantly improved adding formal semantics of different Models of Computation for integrated modelling and verification environments. By bridging this gap, SATURN expects to demonstrate a significant reduction in time-to-market.

This will be delivered through:

• The augmentation of SysML with MARTE
• The use of MARTE as a platform to integate SysML with a run-time environment for cross-domain verification
• The automatic generation of implementable descriptions for both hardware (SystemC/VHDL) and embedded software (C/C++) components of the targeted system
• The integration of different abstraction layers allowing seamless integration at functional and target architecture level.

Results are validated by two complex industrial proof-of-concept case studies covering a smart camera system and an outdoor broadband wireless telecom system.

SATURN combines two SME tool vendors (Artisan and Extessy AG) with leading system houses (Intracom S.A. Telecom Solutions & Thales Security Systems S.A.S). The consortium also includes two major European Universities: Paderborn University & University of Cantabria. SATURN enables Artisan to build on its leading position in engineering based UML tools (extending SysML based on Artisan Studio) while Extessy will benefit from the project by increasing their respective market in verification infrastructures. Taking advantage of the open platform of Extessy AG, the SATURN process will be extremely flexible, and integrate with different third party verification tools and implementations. Through contributions to MARTE standardisation, project results will be exploited both during the project and will persist long after the project has completed.

For an overview presentation see here